Government aims to make 3-nanometre chips by 2032; achieve self-reliance in 75% tech categories in 4 years
GS3Economy · S&T · Environment · Security· IT, AI, semiconductors & computing· Prelims + Mains·
Why in news
Union Minister Ashwini Vaishnaw announced the second phase of the Design-Linked Incentive Scheme aiming for 3-nanometer chip manufacturing by 2032 and 70-75% domestic tech design by 2029.
Background
The government aims to manufacture 3-nanometer chips by 2032 under the second phase of the Design-Linked Incentive Scheme. The initiative targets six chip categories: compute, RF, networking, power, sensor, and memory.
Facts for Prelims
- S&T3-nanometer chips: Target manufacturing goal for India by 2032
- SchemeDesign-Linked Incentive Scheme: Government initiative to develop semiconductor design ecosystem
- FactTarget: 70-75% of technology products to be designed and manufactured domestically by 2029
- FactSix key chip categories: compute, RF, networking, power, sensor, and memory
For Mains
Q. Discuss the significance of developing a domestic semiconductor design ecosystem for India's technological sovereignty and industrial growth.
Dimensions to cover in your answer
- Supply chain resilience: Reducing dependence on global foundry monopolies for high-end 3nm chips
- Incentive structure: Balancing fiscal subsidies with private sector R&D investment in niche chip categories
Keywords: Semiconductor ecosystem · Technological sovereignty · Design-Linked Incentive · Import substitution · Strategic autonomy
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